(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming planarized shallow trench isolation structures in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolation (STI) is now commonly used in the art as an alternative to local oxidation of silicon (LOCOS) for forming isolations between active device areas in the integrated circuit. STI offers the advantages of smaller isolation area and better surface planarization when compared to LOCOS. However, the STI process suffers from dishing, especially over large trenches. Dishing can cause excessive device leakage in some cases. Currently, reverse masking and dummy active structures are the most commonly employed methods to prevent dishing during the STI chemical mechanical polishing (CMP) process. However, reverse masking steps incur additional processing costs. Dummy structures, on the other hand, cause an increase in parasitic capacitance that is not favorable, especially in mixed signal processes.
Co-pending U.S. patent application Ser. No. 09/443,449 to F. Chen, filed on Nov. 22, 1999, teaches a new technique for preventing dishing in an STI process. This technique makes use of a polysilicon layer over the silicon nitride. A CMP slurry having a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 is used in polishing the trench oxide. The technique makes use of the humping effect of the polysilicon polishing to overcome the dishing effect when the nitride is exposed to result in a planarized trench oxide. The polysilicon buffer layer must not be too thin in order to compensate for the dishing effect. Unfortunately, due to etching constraints, the maximum polysilicon buffer thickness is about 1000 Angstroms. If the polysilicon is too thick, the etching aspect ratio is too large. At the end of the STI etch, the photoresist on top of the active area will be completely removed, causing the polysilicon buffer to be etched away during the silicon etch. In addition, if a liner oxidation step is performed, the polysilicon buffer layer will be reduced by half by this oxidation. It is desired to find a way to use this dishing compensation technique with a thick enough polysilicon buffer layer.
Several patents disclose STI processes. U.S. Pat. No. 5,506,168 to Morita et al teaches various methods of forming shallow trench isolation. One embodiment teaches a polysilicon buffer technique, but humping compensation for dishing is not disclosed. Protection of the polysilicon buffer layer is not taught. U.S. Pat. No. 5,712,185 to Tsai et al discloses an STI process in which a polysilicon or oxide layer is used to improve the STI recessed edge. This layer can be removed before CMP. U.S. Pat. No. 5,229,316 to Lee et al teaches a STI process where a sacrificial nitride layer is formed over a polysilicon layer. However, there is no polish stop layer underlying the polysilicon in this process. U.S. Pat. No. 5,837,612 to Ajuria et al teaches another STI process using a polysilicon layer as a polish stop. No silicon nitride is used in this process. U.S. Pat. No. 5,872,045 to Lou et al teaches filling a STI region with polysilicon. U.S. Pat. No. 5,006,482 to Kerbaugh et al teaches polysilicon over oxide and etchback. U.S. Pat. No. 4,307,180 to Pogge teaches a polysilicon layer and an etchback process to prevent dishing.